One of the most critical process control techniques used in the manufacturing of integrated circuits is the measurement of overlay accuracy between successive, patterned layers on a wafer (i.e., the determination of how accurately a patterned layer aligns with respect to the layer above or below it).
Presently this measurement is done with test patterns that are etched into the layers. The relative displacement is measured by imaging the patterns at high magnification on an electronic camera using any of a variety of known image analysis algorithms. The most commonly used patterns are concentric squares with dimensions of approximately 20 micrometers on each side, generally referred to as “box within a box” target. FIG. 1 illustrates a typical “box” type target 5. Inner box 1 is typically printed on the top layer of the semiconductor wafer being produced, while the open-center-outer block 2 is printed on the second layer down on the semiconductor wafer. The measurement process thus involves imaging of target 5 on an electronic camera, by means of a microscope system, at a high magnification (1000×, typically) and with high resolution in both x and y directions.
The registration error in each of the x and y axes is measured by first calculating the locations of the edges of lines c1 and c2 of the outer box 2, and the edge locations of the lines c3 and c4 of the inner box 1. The registration error represents the amount of misalignment between the two layers which are being tested. From those locations the registration error between the two boxes is determined by comparing the average separation between lines cl and c3 with the average separation between lines c4 and c2 (i.e., the registration error between boxes 1 and 2 is the difference between those two separations). The registration error between boxes 1 and 2 in each axis is thus calculated using the following formulas:Rx=(cx3−cx1)−(cx2−cx4)  (1a)andRy=(cy3−cy1)−(cy2−cy4)  (1b)
Thus, if the average spacing between lines c1 and c3 is the same as the average spacing between lines c2 and c4, the corresponding value of R in that axis will be zero.
This prior art is further described and analyzed by Neal T. Sullivan, “Semiconductor Pattern Overlay”, in Handbook of Critical Dimensions Metrology and Process Control, pp. 160–188, vol. CR52, SPIE Press (1993). The accuracy of the prior art is limited by the asymmetry of etched line profiles, by aberrations in the illumination and imaging optics, and by image sampling in the camera. It would be desirable to have a system that overcomes the limitations of the prior art.